Espressif Systems /ESP32-C6 /EXTMEM /L1_CACHE_ACS_CNT_INT_RAW

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Interpret as L1_CACHE_ACS_CNT_INT_RAW

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (L1_IBUS0_OVF_INT_RAW)L1_IBUS0_OVF_INT_RAW 0 (L1_IBUS1_OVF_INT_RAW)L1_IBUS1_OVF_INT_RAW 0 (L1_IBUS2_OVF_INT_RAW)L1_IBUS2_OVF_INT_RAW 0 (L1_IBUS3_OVF_INT_RAW)L1_IBUS3_OVF_INT_RAW 0 (L1_BUS0_OVF_INT_RAW)L1_BUS0_OVF_INT_RAW 0 (L1_BUS1_OVF_INT_RAW)L1_BUS1_OVF_INT_RAW 0 (L1_DBUS2_OVF_INT_RAW)L1_DBUS2_OVF_INT_RAW 0 (L1_DBUS3_OVF_INT_RAW)L1_DBUS3_OVF_INT_RAW

Description

Cache Access Counter Interrupt raw register

Fields

L1_IBUS0_OVF_INT_RAW

The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0.

L1_IBUS1_OVF_INT_RAW

The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1.

L1_IBUS2_OVF_INT_RAW

The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2 due to bus2 accesses L1-ICache2.

L1_IBUS3_OVF_INT_RAW

The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3 due to bus3 accesses L1-ICache3.

L1_BUS0_OVF_INT_RAW

The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache.

L1_BUS1_OVF_INT_RAW

The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache.

L1_DBUS2_OVF_INT_RAW

The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus2 accesses L1-DCache.

L1_DBUS3_OVF_INT_RAW

The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus3 accesses L1-DCache.

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