Cache Access Counter Interrupt raw register
L1_IBUS0_OVF_INT_RAW | The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0. |
L1_IBUS1_OVF_INT_RAW | The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1. |
L1_IBUS2_OVF_INT_RAW | The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2 due to bus2 accesses L1-ICache2. |
L1_IBUS3_OVF_INT_RAW | The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3 due to bus3 accesses L1-ICache3. |
L1_BUS0_OVF_INT_RAW | The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache. |
L1_BUS1_OVF_INT_RAW | The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache. |
L1_DBUS2_OVF_INT_RAW | The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus2 accesses L1-DCache. |
L1_DBUS3_OVF_INT_RAW | The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus3 accesses L1-DCache. |